Exploring Memory Hierarchy Design with Emerging Memory Technologies by Guangyu Sun

Author:Guangyu Sun
Language: eng
Format: epub
Publisher: Springer International Publishing, Cham

1G.(20–100)M.100u

1 GB database, 100 simulated users, the size of buffer pool varies from 20 to 100 MB

The sizes of a page, an erase unit, and a log sector are set to be 4 KB, 256 KB, and 512 Bytes, respectively. For the configuration of the IPL method using only NAND flash memory, there are four log pages in each erase unit. We have mentioned in Sect. 2.4.1 that if the multi-level storage is supported with the PRAM log region, the area of log region is not increased if we replace NAND flash memory with PRAM of the same capacity. In order to explore the advantages of using PRAM, the size of PRAM log region is reduced to be half of the flash log region. Therefore, the area of log region is still kept the same even if the multi-level storage is not employed for the PRAM log region. We will show that performance is still improved. Thus, for the simple static assignment configuration of hybrid architecture, there are 8 KB of PRAM logs in each erase unit. For the dynamic assignment, the merge operations are triggered when the size of free log sectors are lower than 30 % of the total size of PRAM. Then, we ensure that the system will not be stalled for a long time when burst write operations happen.

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